32-bit RISC-V ASIC Design using RTL and HLS

Number of Students : 2
Guide : Kuruvilla Varghese
Sponsor: Intel

This is to design a basic 32-bit RISC-V engine targeted for ASIC after testing on FPGA. The Processor has to be designed using RTL (Verilog) as well as High Level Synthesis (C/C++). The students can modify already designed 32-bit RISC-V Processor for RTL. Comparative study of Area, Power and Throughput need to be done.