32-bit RISC-V Processor on FPGA with RTOS

Number of Students : 1
Guide : Kuruvilla Varghese

Reconfigurable Computing Lab has custom 32-bit Pipelined RISC-V Processor. The Bus interface used is Wishbone. This had to be changed to AXI Bus. Also, all that is lacking in functionality (Necessary Instructions) should be implemented. Presently the system works with Memory inside FPGA. This should be changed to External SRAM/DRAM, also should be able to support Flash memory interface (SD card) for firmware. Finally, a suitable RTOS should be ported to run real time applications.